1. Field of the Invention
The present invention relates to clock generating circuitry for generating a plurality of clocks of different frequencies that differ from the frequency of a reference clock applied thereto.
2. Description of the Prior Art
Referring now to FIG. 3, there is illustrated a block diagram showing the structure of prior art clock generating circuitry. In the figure, reference numeral 1 denotes a phase comparator for comparing the phase of a reference clock fsc applied thereto with that of a frequency-divided clock generated by a frequency divider 5, 2 denotes a charge pump circuit for generating a series of pulses according to the comparison result from the phase comparator 1, and 3 denotes a low-pass filter for attenuating high-frequency components of each of the series of pulses from the charge pump circuit 2 and for furnishing all other low-frequency components to a voltage-controlled oscillator 4. The voltage-controlled oscillator 4 oscillates so as to produce a frequency-multiplied clock of a certain frequency that is proportional to a voltage applied thereto by the low-pass filter 3.
The frequency divider 5 divides the frequency of the frequency-multiplied clock from the voltage-controlled oscillator 4 by 256, and then furnishes the frequency-divided clock to the phase comparator 1. Reference numeral 6 denotes a second frequency divider for dividing the frequency of the frequency-multiplied clock from the voltage-controlled oscillator 4 by 128, and for furnishing the frequency-divided clock as a first clock, and 7 denotes a third frequency divider for dividing the frequency of the frequency-multiplied clock from the voltage-controlled oscillator 4 by 227, and for furnishing the frequency-divided clock as a second clock.
In operation, in the case that PAL is adopted as a television system, there is a need to generate a clock for video signal generation and another clock for VPS (text broadcasting or teletext used in Europe), and the chrominance subcarrier for PAL whose frequency is about 4.43 MHz is used as the reference clock fsc.
When the phase comparator 1 receives the reference clock fsc whose frequency is about 4.43 MHz, it compares the phase of the reference clock fsc with that of the frequency-multiplied clock furnished by the voltage-controlled oscillator 4 so as to make them be in phase with each other. When the phase of the reference clock fsc is delayed with respect to that of the frequency-multiplied clock, the charge pump 2 generates one or more low-state pulses throughout a period during which the phase delay lasts, that is, until their phases are made to be in phase with each other, so as to introduce phase lag into the frequency-multiplied clock. The low-pass filter 3 then attenuates high-frequency components of each low-state pulse from the charge pump, and lowers its voltage that will be applied to the voltage-controlled oscillator 4. As a result, the voltage-controlled oscillator 4 can delay the phase of its output. Finally, the frequency-multiplied clock from the voltage-controlled oscillator 4 is made to be in phase with the reference clock fsc.
In contrast, when the phase of the reference clock fsc leads that of the frequency-multiplied clock from the voltage-controlled oscillator 4, the charge pump 2 generates one or more high-state pulses throughout a period during which the phase lead lasts, that is, until their phases are made to be in phase with each other, so as to introduce phase lead into the frequency-multiplied clock. The low-pass filter 3 attenuates high-frequency components of each high-state pulse from the charge pump, and raises its voltage that will be applied to the voltage-controlled oscillator 4. As a result, the voltage-controlled oscillator 4 can introduce phase lead into its output. Finally, the frequency-multiplied clock from the voltage-controlled oscillator 4 is made to be in phase with the reference clock fsc.
In this manner, the voltage-controlled oscillator 4 generates a frequency-multiplied clock whose frequency depends on the output voltage of the low-pass filter 3. The frequency-multiplied clock generated by the voltage-controlled oscillator 4 can have a frequency 256 times (about 1.1 GHz) as high as that (about 4.43 MHz) of the reference clock fsc only if the frequency-multiplied clock is in phase with the reference clock fsc.
When the voltage-controlled oscillator 4 oscillates to generate the frequency-multiplied clock having a frequency of about 1.1 GHz, the second frequency divider 6 generates a clock of a frequency two times as high as that of the reference clock fsc (the video signal requires a clock of a frequency two times as high as that of the reference clock fsc because color information is piggybacked onto the video signal by phase-modulating the chrominance subcarrier). In other words, the second frequency divider 6 divides the frequency of the frequency-multiplied clock from the voltage-controlled oscillator by 128 so as to generate the first clock whose frequency is about 8.86 Mhz (1.1 GHz/128 is nearly equal to 8.86 MHz).
When the voltage-controlled oscillator 4 oscillates to generate the frequency-multiplied clock having a frequency of about 1.1 GHz, the third frequency divider 7 generates a clock of a frequency 320 times as high as that of the horizontal synchronizing signal (15.625 MHz) (VPS signal requires a clock of a frequency 320 times as high as that of the horizontal synchronizing signal). In other words, the third frequency divider 7 divides the frequency of the frequency-multiplied clock from the voltage-controlled oscillator by 227 so as to generate the second clock whose frequency is about 5.00 MHz (1.1 GHz/227 is nearly equal to 5.00 MHz).
Japanese Patent Application Publication (KOKAI) No. 7-336217 discloses an apparatus in which a first PLL, a frequency divider, and a second PLL are connected in series to reduce the time required to lock up the PLLs and improve the stability of the locking of the PLLs. However, the apparatus does not employ the PAL system as a television system, and the reference does not disclose a technique for setting a ratio of frequency division in each circuit to a proper value.
A problem with such prior art clock generating circuitry so constructed as mentioned above is that although the voltage-controlled oscillator 4 can theoretically generate a clock for video signal generation and another clock for VPS by dividing the frequency of the reference clock fsc by 256, it is actually difficult to provide such the voltage-controlled oscillator that can generate a frequency-multiplied clock of a very high frequency (for example, about 1.1 GHz).